The present invention relates to a read-only memory (ROM) device, more particularly, to the output portion of a large capacity ROM device such as a mask ROM device or an EPROM (erasable programmable ROM) device.
In a mask ROM device, the binary data "0" or "1" of a memory cell at each intersection between word lines and bit lines corresponds to:
the presence or absence of an enhancement type transistor;
the high or low threshold voltage of a transistor;
the enhancement type or depletion type of a transistor; or
the presence or absence of a contact window (throughhole) which connects one of the bit lines to a transistor.
Similarly, in an EPROM device, the binary data "0" or "1" of a memory cell corresponds to the high or low threshold voltage of a transistor, which is determined by injecting carriers into a floating-gate due to the tunnel effect or avalanche breakdown. In any ROM device, since a memory cell serves only as a switch, a memory cell has no driving power for charging a corresponding bit line during the read mode. Therefore, one or more load elements are necessary for charging the bit lines during the read mode.
According to a first conventional ROM device, a plurality of switching transistors (gates) are provided between bit lines and data bus lines which are connected to a sense amplifier. When one of the switching transistors is selected by a group of column address decoders, the selected transistor is turned on so as to connect one of the bit lines to one of the data bus lines. As a result, one bit line is connected through the selected switching transistor to the sense amplifier. In this case, a load element is provided in the sense amplifier, so as to charge the selected bit line and all the data bus lines, that is, pull up the potentials of these lines. During the read mode, for one memory cell, the potential of a word line corresponding to this cell is selected and connected to the sense amplifier. As a result, the potential of the selected bit line is decreased or retained in accordance with the on-state or off-state of the memory cell. Thus, the memory data thereof is read out at the sense amplifier.
In such a ROM device, if it is of a small capacity such as 16 kbits and 65 kbits, the load capacity of the data bus lines driven by one load element is not large enough to cause a problem.
However, in a large capacity ROM device such as a 256 kbit device, the number of bit lines, the number of switching transistors, and the number of the data bus lines is increased. As a result, to increase the pulling-up speed of the potentials of the selected bit line and the data bus lines, the driving power or conductance g.sub.m of the load element must increase. On the other hand, since the area of a memory cell becomes small, the conductance g.sub.m of an on-state memory cell also becomes small. As a result, the dimensions of the switching transistors must be large and, in addition, the conductance g.sub.m of the load element must decrease, since the ratio of the conductance g.sub.m of the on-state memory cell to that of the load element must be definite to ensure a reliable read operation. It is difficult to increase the driving power or conductance g.sub.m of the load element and, also to perform rapid pulling-up of the potentials of the bit lines and the data bus lines to perform a high speed read operation.
According to a second conventional ROM device, bit lines are divided into a plurality of groups. One bit line within each group is selected by first column address decoders and, in addition, one group is selected by second column address decoders. As a result, one selected bit line is connected to one of the data bus lines. Compared with the first conventional device, the load capacity driven by the load element becomes small, and the driving power of the load element in the sense amplifier may be small. However, even in this case, since only one load element is provided, it is difficult to perform rapid pull-up of the potential of the bit lines and the data bus lines and, accordingly, to perform a high speed read operation in a large capacity ROM device, such as a 256 kbit device.